FIGS. 1A-1G show the manufacturing steps for creating a conventional vertical LED (VLED) chip. In FIGS. 1A and 1B, an epitaxial growth process forms an N-type epitaxial semiconductor layer 101 on a semiconductor growth substrate 100, such as sapphire (Al203). In FIG. 1C, an epitaxial growth process forms a P-type epitaxial semiconductor layer 102 on top of the N-type epitaxial semiconductor layer 101. In FIG. 1D, a metal bonding layer 103 is deposited on top of the P-type epitaxial semiconductor layer 102. The metal bonding layer 103 is a conductive material, for example gold tin (AuSn), nickel tin (NiSn), copper tin (CuSn), and silicon gold (SiAu), and may comprise multiple conductive layers made of different types of conductive materials, including a mirror layer (not pictured). The mirror layer generally comprises a material having a high degree of reflectivity, for example aluminum (Al), silver (Ag), or Rhodium (Rh).
In FIG. 1E, a conventional wafer bonding process, such as eutectic bonding where heat and pressure are used to form an ohmic connection, bonds a first surface 104a of a carrier substrate 104 to the metal bonding layer 103. The carrier substrate 104 may be made of single crystal materials such as silicon, sapphire, or silicon carbide, or ceramic materials, such as aluminum nitride, silica, or metallic materials having good heat conductivity such as aluminum, copper, nickel, or alloys thereof. In FIG. 1F, the semiconductor growth substrate 100 has been removed. Removal of the semiconductor growth substrate 100 may be accomplished by any known method, including Laser Lift Off (LLO) or chemical etching. In FIG. 1G, a deposition and etching process forms an N-electrode 105 and a P-electrode 106 on opposite sides of the VLED chip. The N-electrode 105 is formed on the N-type epitaxial semiconductor layer 101 and the P-electrode 106 is formed on a second surface 104b of carrier substrate 104.
The VLED chip allows for greater light extraction efficiency than the traditional LED chip because the photons that are emitted downward from the LED to carrier substrate 104 are reflected back upwards by the metal bonding layer 103 and optional mirror layer, allowing them to escape rather than being absorbed. Other benefits of the VLED chip include improved heat dissipation and current spreading due to the use of a carrier substrate with high thermal conductivity and the vertical current flow through the LED, respectively.
An LED chip typically must be packaged before it can be used in an application. Packaging of an LED device such as a VLED chip for use in a lighting system application often includes attaching an encapsulant dome lens over the top surface of the LED device. Besides protecting the LED device, the dome lens improves the light emitting efficiency of the LED device. FIG. 2A is a cross-sectional diagram of a prior art LED package 200 having an encapsulant dome 216. LED package 200 includes a carrier substrate 210, an LED device 212, a phosphor-containing layer 214, and an encapsulant dome 216. Carrier substrate 210 is made of single crystal materials such as silicon, sapphire, or silicon carbide, or ceramic materials, such as aluminum nitride, silica, or metallic materials having good heat conductivity such as aluminum, copper, nickel, or alloys thereof. LED device 212 can be any type of light emitting diode structure, including an LED device made using a vertical chip process as described above. A metal bonding layer (not shown) bonds LED device 212 to carrier substrate 210. Phosphor-containing layer 214 is a conformal layer formed over LED device 212. Phosphor-containing layer 214 is typically a mixture of highly transparent silicone with phosphor particles therein. Phosphor-containing layer 214 modifies the wavelength of the light emitted by LED device 212 to “whiten” the light emitted by LED package 200.
Dome 216 is made of a transparent material, such as silicone, and enhances the light extraction efficiency of the device. Dome 216 is hemispherical and provides a highly directional emission pattern in which the majority of the emitted light is close to the optical axis of LED device 212. FIGS. 2B and 2C are graphs of a far-field emission pattern of the LED package 200 of FIG. 2A, in polar and Cartesian coordinates, respectively. Both FIGS. 2B & 2C show values of radiant intensity expressed as power per unit solid angle (W/sr). As can be seen in FIGS. 2B & 2C, the intensity is at a maximum near the optical axis (0°) of the LED device 212. The values in FIGS. 2B & 2C are for an LED package 200 with a LED device having a footprint of 1 mm2 and a dome 216 with a radius of 4 mm.
In LED packages having a dome, the radius of dome 216 must be larger than the length 218 of LED device 212 to achieve the maximum light extraction efficiency, which means that the diameter of dome 216 must be significantly larger than the length 218 of LED device 212. Because the radius of dome 216 is larger than the length 218 of LED device 212, the footprint area of dome 216 is necessarily significantly larger, typically at least 2-3 times larger, than the footprint area of LED device 212. A dome of this size thus necessitates that carrier substrate 210 have a surface area that is also at least 2-3 times larger than the footprint of LED device 212.
While dome 216 is effective in enhancing the light extraction efficiency of LED package 200 and providing a directional emission pattern close to the optical axis, one drawback of dome 216 is that it is impractical to include formation of such a large dome in a full wafer level packaging scheme because of the large difference between the footprint of LED device 212 and the completed LED package 200. Another drawback is that such a relatively large dome requires a large volume of transparent silicone material, which is a significant portion of the manufacturing cost of the completed device.
Thus, there is a need for an LED package having an encapsulant lens that is more efficient and less expensive to manufacture than an LED package with a dome lens without sacrificing light extraction efficiency.